Many transmitters, such as early Bluetooth on-chip transmitter designs, were based on a “Cartesian Loop” transmitter/receiver design. However, this design has a number of drawbacks due to the relatively high content of analogue circuitry that they contain. As silicon processes shrink and are further optimised for digital circuitry, these drawbacks increase.
A more recent transmitter design is the polar transmitter, as shown in FIG. 1. The input signals are encoded to produce two output signals, one (θ) conveying frequency information and the other (r) conveying amplitude information. The frequency information signal is fed into a phase locked loop (PLL) which controls the generation of a signal of a corresponding frequency by an oscillator and the amplitude information signal is fed into an amplitude modulator (AM). The output of the oscillator is then amplitude modulated by the signal r.
The PLL typically consists of the following blocks                An oscillator whose frequency is controlled by a signal of some sort. The oscillator is typically a voltage controlled oscillator, whose output frequency is controlled by an input voltage.        A phase comparator, to compare the phase of the VCO output—perhaps after division—with an input reference frequency. If the phase of an output related signal is locked to a reference, its differential (its frequency) is ipso facto locked.        A loop filter. For the overall loop to be stable and usable, a loop filter is implemented.        
In analogue PLLs the phase comparator is difficult to design so as to meet the desired tolerances whilst maintaining acceptable power consumption.
Particularly because of the way processes are optimised, it is attractive that both the PLL and the AM are implemented in digital form, and are controllable using digital input signals. However, it has proved difficult to implement digital forms of these components in practice.
A Texas Instruments digital PLL design (“All-digital Tx frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS”, Staszewski, Muhammad, Leipold, Hung Ho, Wallberg, Fernando, Maggio et al.) provides a VCO that is controlled by a digital word (a very wide digital word), and a phase detection system that achieves very fine phase resolution. However, this circuit is relatively complex.
There is therefore a need for a PLL that is more readily implemented and that has relatively low power consumption. Preferably such a PLL could be readily integrated with an amplitude modulator, so that the amplitude can be controlled using a digital input.
According to one aspect of the present invention there is provided a phase locked loop and an amplitude modulator as set out in the accompanying claims.